1. Field of the Invention
This invention relates generally to serial addressing of memory chips and in particular to a method and apparatus for using a chain selection scheme in a fault-tolerant mode for addressing a plurality of arrays, each of which contains a plurality of serial registers, on CCD chips.
2. Description of the Prior Art
In order to effectively utilize CCD technology, high density must be obtained. The smallest possible cell sites for storage of charge is desirable, as well as an optimum spacial configuration of cell sites forming a register in order to achieve the high density. In practical applications of CCDs, the density problem is present not only at a configurational level within the register, but also with respect to control circuitry for interfacing between the registers and the remainder of the data processing system. High density CCD storage registers are described in Related Application Nos. 1 and 2. Injector, sense amplifier, and interface circuitry for each register are described in Related Application Nos. 3, 4, and 5 respectively.
In order to achieve the desired density levels, concern for minimization of spacial requirements must extend to a configurational level beyond that of the register. For example, registers may advantageously be grouped in parallel to form arrays. Whenever, an array is accessed, all of the registers work in parallel, that is, they READ, WRITE or REFRESH simultaneously over a plurality of data buses. In this manner, control circuitry is used for a plurality of registers and is thereby minimized, increasing the effective density of the CCD chip containing the registers. Such a high chip configuration and associated control circuitry is described in Related Application No. 6. In this manner, a chip receives an address corresponding to a single array and proceeds to address in parallel the plurality of registers comprising that array. Each of the registers then transmits the data within it serially, since the CCD registers are serial storage devices. Requirements of such a system therefore include an addressing scheme for the arrays on the chips forming a memory module.
Whenever data is to be accessed (read) or stored (written), it is necessary to address the memory area where the date is, or is to be, stored. This requires some form of addressing scheme. Two basic types of addressing schemes are serial and parallel. Serial addressing requires only one lead or wire to the storage unit. However, data bits transmitted over this lead must be multiplexed over time, and before their usage as an address, they generally require some form of demultiplexing. Serial addressing offers advantages of simplicity of design, and lesser area and power requirements. However, it is generally a relatively slow method, since it requires transmission of the address bit-by-bit, until all of the address bits have been transmitted.
Parallel addressing requires a plurality of leads for simultaneous transmission of bits over these leads. In this manner, the address is rapidly transmitted to the memory area. However, since many lines are required, much space as well as additional power to transmit all of these bits in parallel is required.
Once an address is transmitted to a memory area, whether it be by serial or parallel method, this address must be used in some way to determine which area within the memory is to be accessed. Prior art methods utilized stored addresses for each storage area. For example, each array had a stored address uniquely corresponding to that array. This stored address was compared to the input address to determine if they were the same. If so, the array corresponding to this stored address was accessed. However, this method required not only holding of stored addresses, but also a holding area for the input address, and a comparator for operating on the two addresses. All these requirements obviously add to the spacial requirments of embodiments for this method.
Most prior art addressing schemes assume that all parts of the memory system whether it be on a chip or some other form of system, are 100% operational. In this manner, each area is assumed to have a unique address and each address corresponds to a working and utilizable data area. However, at a chip level, 100% working capability of storage parts implies a very high processing cost for chips. If a chip could contain areas, such as arrays, some of which were defective, substantial cost savings could result. However, this would require a fault-tolerant addressing scheme, that is, one which avoided the malfunctioning arrays. There are, in general, two ways of avoiding addressing of defective storage areas. One is by software control. However, this requires storing the addresses corresponding to defective storage areas in some part of the system and then comparing an address to this stored address in order to avoid addressing of a defective area. Clearly, this is a slow and costly way of achieving fault-tolerance, A more desirable way is by a hardware scheme which automatically prevents addressing of the defective areas.